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2.5 msps, 20-bit ? adc prelim inary technical data ad7760 rev. pr n in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features high performance 20-bit sig m a-delt a adc 118db s n r at 7 8 khz output d a ta rate 100db s n r at 2 . 5mhz output data rat e 2.5 mhz maxim u m fu lly filtere d output word rate programmable over-sampling rate (8x to 256x) flexible parall el interface fully dif f erenti al modul a tor input on-chip differe ntial amplifier for signal buffe ring low pass fir filter with def a ul t or user programmable coefficients over-range ale r t bit digital offset a n d gain correction registers filter bypass m o des low power and power down modes synchronization of multiple devices via sync pin applic ati o ns data acq u isitio n systems vibration anal ysis instrumentation func tio n a l block di agram diff multi-bit sigma-delta modulator ad7760 contr o l logic, i/o and register s reconstruction pr ogrammab l e decimation fir filter engine db0 - db15 vin+ vin- av dd1 a gnd vref+ mclk wr drd y dgnd bu f v drive
av dd2 av dd3 av dd4 dv dd - + decap r bias fi g u r e 1 . product overview the ad7760 hig h p e r f o r ma n c e 20-b i t sig m a del t a a n alog t o dig i t a l con v er te r co m b i n es wid e in p u t b a ndwi d t h and hig h s p ee d w i t h th e ben e f i ts o f si gm a d e l t a co n v e r sio n wi th p e r f o r ma n c e o f 100db s n r a t 2 . 5ms p s makin g i t ideal f o r hig h sp e e d da t a ac q u isi t io n. w i de d y na mic r a n g e com b i n e d wi t h si gn i f i c a n tl y r e d u ced a n ti - a li a s in g r e q u i r em e n ts si m p li f y th e desig n p r o c es s. an in t e g r a t e d b u f f er t o dr i v e t h e r e fer e n c e , a dif f er en t i a l a m plif ier fo r sig n a l b u f f er in g a nd le v e l shif t i ng, a n ove r - r ange f l a g , i n te r n a l g a i n & of f s e t re g i ste r s an d a l o w - p a ss dig i t a l fir f i l t er mak e the ad7 760 a co m p ac t hig h l y in t e g r a t e d d a t a a c q u isi t ion de vice r e q u ir ing minim a l p e r i ph era l co m p on e n t s e le c t io n. i n a d d i t i on t h e d e vi ce o f fers p r o g r a mma b l e de cim a t i o n r a te s a nd t h e d i g i t a l f i r f i l t er ca n b e ad j u s t e d if t h e defa u l t cha r ac t e r i s t ics a r e n o t a p pr o p r i a t e t o t h e a p p l ic a t ion. th e ad7760 is ide a l f o r a p p l ica t ions deman d in g hig h snr w i t h ou t ne cessi t a t in g desig n o f co m p l e x f r o n t en d sig n al p r o c es sing. the dif f er en t i al in p u t is s a m p le d a t u p t o 40ms / s b y a n a n alog m o d u l a t o r . th e m o d u l a t o r o u t p u t is p r o c es s e d b y a s e r i es o f lo w-p a s s f i l t ers, t h e f i nal on e ha vin g def a u l t o r us er p r og ra mma b l e co ef f i cien ts. the s a m p le r a t e , f i l t er co r n er f r e q uen c ies and o u t p u t w o r d ra t e a r e s e t b y a c o m b in a t ion o f t h e ext e r n al clo c k f r e q uen c y and t h e co nf igura t io n r e g i s t ers o f th e ad7760. the r e f e r e n c e vol t a g e s u p p lie d t o th e ad7760 det e r m in es t h e an a l o g i n put r a nge. w i t h a 4 v re f e re nc e, t h e a n a l o g i n put r a n g e is 3.2v dif f er en t i al b i as e d a r o u n d a co mm on m o de o f 2v . thi s co mm o n m o de b i asin g ca n b e ac hiev e d usin g t h e on-c hi p dif f er en t i al a m plif iers, f u r t h e r r e d u cin g t h e exter n al sig n al co ndi t i onin g r e q u ir em e n ts . the ad7760 is a v a i la b l e in an exp o s e d p a ddle 64-lead t q fp a nd 48-le a d csp p a cka g es and is sp e c if ie d o v er t h e i n d u st r i a l t e m p era t ur e ra ng e f r o m -40c to +85c.
ad7760 preliminary technical data rev. prn | page 2 of 22 table of contents table of contents .................................................................. 2 ad7760specifications .................................................................. 3 timing specifications ....................................................................... 5 timing diagrams .............................................................................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and functional descriptions .......................... 8 te r m i no l o g y .................................................................................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 12 ad7760 interface ............................................................................ 13 clocking the ad7760 ..................................................................... 14 driving the ad7760 ...................................................................... 15 using the ad7760 ..................................................................... 16 bias resistor selection ............................................................... 16 programmable fir filter ............................................................... 17 downloading a user-defined filter ............................................ 18 example filter download ......................................................... 18 ad7760 registers ........................................................................... 20 non bit-mapped registers ........................................................ 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history
preliminary technical data ad7760 rev. prn | page 3 of 22 ad7760specifications table 1. v dd1 = 2.5 v, v dd2 = 5 v, v ref = 4.096 v, t a = +25c, full power mode, unless otherwise noted parameter test conditions/comments specifcation unit dynamic performance decimate by 256 mclk = 24.576mhz, odr = 48khz, fin = 1khz sine wave signal to noise ratio (snr) 1 118 db typ spurious free dynamic range (sfdr) 1 non-harmonic 118 dbfs typ total harmonic distortion (thd) 1 input amplitude = -6db -100 db typ intermodulation distortion (imd) 1 -100 db typ decimate by 16 mclk = 40mhz, odr = 1.25mhz, fin =100khz sine wave signal to noise ratio (snr) 1 103 db typ spurious free dynamic range (sfdr) 1 non-harmonic 103 dbfs typ total harmonic distortion (thd) 1 input amplitude = -6db -100 db typ intermodulation distortion (imd) 1 -100 db typ decimate by 8 mclk = 40mhz, odr = 2.5mhz, fin = 100khz sine wave signal to noise ratio (snr) 1 100 db typ spurious free dynamic range (sfdr) 1 non-harmonic 100 dbfs typ total harmonic distortion (thd) 1 input amplitude = -6db -100 db typ intermodulation distortion (imd) 1 fin = 100khz sine wave -100 db typ intermodulation distortion (imd) 1 fin = 1mhz sine wave -100 db typ dc accuracy resolution 20 bits integral nonlinearity 1 at 18 bits 1 lsb typ differential nonlinearity 1 guaranteed monotonic to 20 bits 1 lsb typ offset error 1 0.03 % typ gain error 1 5 lsb typ offset error drift 0.0006 % /c gain error drift 0.1 lsb /c digital filter response decimate by 8 group delay mclk = 40mhz 12 s typ decimate by 16 group delay mclk = 40mhz 24 s typ decimate by 128 group delay mclk = 24.576mhz 480 s typ analog input differential input voltage vin(+) C vin(-), v ref = 2.5v 2 v pk-pk vin(+) C vin(-), v ref = 4.096v 3.25 v pk-pk dc leakage current 2 a max input capacitance with in ternal buffer 5 pf typ with external buffer 55 pf typ reference input/output v ref input voltage v dd3 = 3.3v +2.5 volts v dd3 = 5v +4.096 volts v ref input dc leakage current 1 a max v ref input capacitance 5 pf max power requirements av dd1 (modulator supply) 5% +2.5 volts av dd2 (general supply) 5% +5 volts av dd3 (diff-amp supply) +3.0/+5.5 v min/max av dd4 (ref buffer supply) +3.15/+5.25 v min/max dv dd 5% +2.5 volts v drive +1.65/+2.7 v min/max
ad7760 preliminary technical data rev. prn | page 4 of 22 parameter test conditions/comments specifcation unit full power mode ai dd1 (modulator) 50 ma typ ai dd2 (general) 35 ma typ ai dd4 (reference buffer) av dd4 = +5v 35 ma typ low power mode ai dd1 (modulator) 26 ma typ ai dd2 (general) 20 ma typ ai dd4 (reference buffer) av dd4 = +5v 10 ma typ ai dd3 (diff amp) av dd3 = +5v, both modes 42 ma typ d idd both modes 45 ma typ standby mode ai dd1 (modulator) 210 a typ ai dd2 (general) 30 na typ ai dd3 (diff amp) av dd3 = +5v 30 na typ ai dd4 (reference buffer) av dd4 = +5v 30 na typ d idd clock stopped 250 a typ clock running 690 a typ power dissipation full power mode modulator (p 1 ) 125 mw typ general (p 2 ) 175 mw typ reference buffer (p 4 ) av dd4 = +3.3v 101 mw typ av dd4 = +5v 175 mw typ low power mode modulator (p 1 ) 65 mw typ general (p 2 ) 100 mw typ reference buffer (p 4 ) av dd4 = +3.3v 27 mw typ av dd4 = +5v 50 mw typ differential amplifier (p 3 ) av dd3 = +3.3v 116 mw typ av dd3 = +5v 210 mw typ digital power 112.5 mw typ standby mode clock stopped 1.2 mw typ clock running 2.3 mw typ 1 see terminology
preliminary technical data ad7760 rev. prn | page 5 of 22 timing specifications table 2. v dd1 = 2.5 v, v dd2 = 5 v, v ref = 4.096 v, v drive = tbd v, t a = +25c, c load = 25pf, full power mode, unless otherwise noted parameter limit at t min , t max unit description f mclk 12.288 mhz min applied master clock frequency 80 mhz max f iclk 12.288 mhz min internal modulato r clock derived from mclk. 20 mhz max t 1 1 0.5 t iclk typ drdy pulse width t 2 10 ns min drdy falling edge to cs falling edge t 3 2 ns min rd /wr setup time to cs falling edge t 4 10 ns typ data access time t 5 t iclk min cs low pulse width t 6 t iclk min cs high pulse width between reads t 7 2 ns min rd /wr hold time to cs rising edge t 8 10 ns max bus relinquish time t 9 0.5 t iclk typ drdy high period t 10 0.5 t iclk typ drdy low period t 11 15 ns typ data access time t 12 tbd xs min data valid prior to drdy rising edge t 13 tbd xs min data valid after drdy rising edge t 14 10 ns max bus relinquish time t 15 t iclk xs min cs low pulse width t 16 t iclk xs min cs high period between address and data t 17 10 ns min data setup time t 18 10 ns min data hold time 1 t iclk = 1/f iclk
ad7760 prelim inary technical data r e v. prn | pa ge 6 o f 22 timing diagrams f i gure 2. p a r a ll el in ter f a c e t i mi ng d i a g r a m
f i g u re 3. 20m h z m o dul a t o r d a t a o u t p ut m o de f i g u re 4. a d 77 60 r e g i s t e r writ e
prelim inary technical data ad7760 r e v. prn | pa ge 7 o f 22 absolute maximum ra tings t a bl e 3. t a = 2 5 c, un l e s s ot h e r w i s e not e d. p a r a m e t e r s r a t i n g v dd to gnd tbd v in+ to gnd tbd v inC to gnd tbd digital input voltage to gnd tbd digital output v o ltage to gnd tbd v ref to gnd tbd input current to any pin exce pt s u pplies 1 tbd operating temperature range commercia l ( a , b versio n ) ?40c to +85c storage temperature range ?65c to +150c junction tempe r ature 150c tqfp exposed paddle package ja thermal impedance 92.7 c/w jc thermal impedance 5.1 c/w csp package ja thermal impedance 26.7 c/w jc thermal impedance 30 c/w lead temperature, soldering vapor phase (60 secs) 215c infrared (15 secs) 220c e s d t b d k v 1 transient currents of up to t b d ma do not cause s c r latch-up. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7760 prelim inary technical data r e v. prn | pa ge 8 o f 22 pin conf igura t ion and fu nctional descri ptions db8 db9 db10 db11 decap2 decap3 agnd agnd agnd av dd2 av dd2 agnd db12 db13 db14 db15 v drive dgnd dgnd dv dd /wr 39 38 37 41 40
dgnd agnd av dd1 36 35 34 33 42 43 44 45 46 47 48 17 1 8 19 20 21 22 2 3 24 r bias agnd v in a1+ v in a1- v out a1- v out a1+ agnd av dd3 v in + v in - av dd2 agnd 1 2 3 4 5 6 7 8 9 10 11 12 6 4 63 6 2 61 60 5 9 58 v drive dgnd dgnd db0 db1 db2 db3 db4 db5 db6 db7 dgnd pin 1 identifier top view (not to scale) ad7760 dgnd mclk av dd2 av dd1 agnd v ref+ agnd av dd4 13 14 15 16 25 26 27 31 30 29 28 32 57 56 55 54 53 52 51 50 49 agnd decap1 refgnd f i gure 5. 64-l e ad t qfp pin configu r ation db15
ad7760 top view (not to scale) v drive mclk av dd2 av dd1 refgnd
av dd4 av dd2 av dd2
av dd3 av dd2 av dd1
/wr dv dd v drive db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 f i g u r e 6. 48- pin lfcsp pin conf ig u r at ion t a bl e 4. p i n f u nc ti on des c ripti o ns tqfp pin number csp pin number pin mnemonic description 6, 33 5, 25 av dd1 +2.5v power su pply for modulator. these pins sh ould be decoupled to agnd with 100nf and 10f capacitor s on each pin. 4, 14, 15, 27 4, 10, 11, 20 av dd2 +5v power sup p ly. t h ese pin s s h ould be d e coupled to agnd with t b d nf and tbd f capacitor s on ea ch pin. 2 4 1 7 av dd3 +3.3v to +5v power supp ly for d i fferential amp l i f ier. t h ese pins s h ould be d e coupled to agnd with a 100nf capacitor. 1 2 9 av dd4 +3.3v to +5v power supply for reference buffer. th is pin sh ould be d e coupled to agnd with a 10nf capacitor i n series with a 22 ? resistor. 5, 7, 11, 13, 16, 18, 23, 28, 31, 32, 34 23, 24, paddl e agnd power supply ground for analog circuitry. in the chip scale pack age, most of the internal agnd pads are dow n -bonded t o the ex pos e d p a ddle. this paddle then becom e the main analog ground connection for the ad7760. 9 7 refgnd reference ground. ground connection for the r e ference vo ltage. 4 1 3 1 dv dd +2.5v power su pply for digital circuitry and fir filter. t h is pin sh ould be d e coupl e d to dgnd with a 470nf capacitor. 44, 63 1, 32 v drive logic power supply input, +1.8 v to +2.5v. t h e voltage supp lie d at these pins will d e termine the operating voltage of the logic interface. bo th these pins must be connecte d together and tied to the same supply. each pi n should al so be decoupled to dgnd with a 470 nf capacitor. 1, 35, 42, 43, 53, 62, 64 p a d d l e d g n d ground reference for digital circuitry. in the chi p scale p a ckage , all the interna l dgnd pads are down-b onded to the exposed paddle. this paddle then bec o mes the sing le ground connection for the ad7760.
preliminary technical data ad7760 rev. prn | page 9 of 22 tqfp pin number csp pin number pin mnemonic description 19 13 v in a1+ positive input to full-power differential amplifier 1. 20 14 v in a1- negative input to full-power differential amplifier 1. 21 15 v out a1- negative output from full-power differential amplifier 1. 22 16 v out a1+ positive output from full-power differential amplifier 1. 25 18 v in + positive input to the modulator. 26 19 v in - negative input to the modulator. 10 8 v ref+ reference input. the input range of this pin is determined by the reference buffer supply voltage (av dd4 ). see reference section for more details. 8 6 decap1 decoupling pin. a 100nf capacitor must be inserted between this pin and agnd. 29 21 decap2 decoupling pin. a tbd f capacitor must be inserted between this pin and agnd. 30 22 decap3 decoupling pin. a tbd f capacitor must be inserted between this pin and agnd. 17 12 r bias bias current setting pin. a resistor must be inserted between this pin and agnd. for more details on this, see the bias resistor section. 45-52, 54-61 33-48 db15 C db0 16-bit bi-directional data bus. these are th ree-state pins that are controlled by the cs and rd /wr pins. the operating voltage for these pins is determined by the v drive voltage. see interfacing section for more details. 37 27 reset a falling edge on this pin resets all internal digital circuitry. holding this pin lows keeps the ad7760 in a reset state. 3 3 mclk master clock input. a low jitter digital clock must be applied to this pi n. the output data rate will depend on the frequency of this clock. see clocking section for more details. 2 2 mclk master clock ground sensing pin. 36 26 sync synchronization input. a falling ed ge on this pin resets the intern al filter. this can be used to synchronize multiple devices in a system. 39 29 rd /wr read/write input. this pin, in conjunction with the chip select pin, is used to read and write data to and from the ad7760. if this pin is low when cs is low, a read will take place. if this pin is high and cs is low, a write will occur. see ad7760 interface section for more details. 38 28 drdy data ready output. each time that new conver sion data is available, an active low pulse, ? iclk period wide, is produced on this pin. see ad7760 interface section for further details. 40 30 cs chip select input. used in conjunction with the rd /wr pin to read and write data to and from the ad7760. see ad7760 interface section for further details.
ad7760 prelim inary technical data r e v. prn | pa ge 10 of 22 terminology si g n a l to ( n oi s e + d i s t or t i on ) r a t i o t h e me a s u r e d r a t i o of s i g n a l to ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a d c. th e sig n al i s t h e r m s am pli t ude o f t h e f u ndam e n t a l . n o is e is t h e sum o f a l l n o nf u ndam e n t a l sig n a l s up t o half th e s a m p lin g f r e q uen c y (f s /2), excl udin g dc. the ra t i o is dep e n d e n t on t h e n u m b er o f q u a n t i za t i on le vels in t h e d i gi t i za ti o n p r o c e s s; th e m o r e lev e l s, th e sm alle r th e q u a n tiz a ti o n n o i s e . th e t h eo r e tical si gn al t o (n o i se + d i s t o r ti o n ) ra tio f o r a n id ea l n-b i t co n v er t e r wi t h a sin e wa v e in p u t is gi v e n by ( ) ( ) db n distortion noise to signal 76 . 1 02 . 6 + = + th us, f o r a n 18-b i t con v er t e r , this is 110.12dbs a nd f o r a 20-b i t co n v er t e r , 122.16 db . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h e r a t i o of t h e r m s su m of h a r m on i c s to t h e f u n d a me n t a l . f o r th e ad7760, i t is def i ned as () 1 2 6 2 5 2 4 2 3 2 2 v v v v v v 20 db thd + + + + = log w h er e: v 1 is t h e r m s am pli t ude o f t h e f u ndam e n t al . v 2 , v 3 , v 4 , v 5 , a nd v 6 a r e t h e r m s a m pli t udes o f t h e s e con d t o t h e sixt h ha r m o n i c s . p e a k h a rmo n i c o r s p uri o us n o is e the ra t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p u t s p ec tr um (u p t o f s /2 an d excl uding dc) to t h e r m s val u e o f t h e f u ndam e n t al . n o r m al l y , t h e val u e o f t h is sp e c if ic a t ion is det e r m i n e d b y t h e la rgest ha r m o n ic in t h e s p e c t r um, b u t, fo r ad cs w h er e t h e ha r m o n ics ar e b u r i e d i n t h e n o is e f l o o r , i t is a n o i s e p e a k . n o n - h a rmo n ic s p u r io u s f r ee d y n a m i c ra n g e ( s f d r ) the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e p e ak sp ur io us s p ec tral co m p onen t exc l udin g ha r m o n ics. inte r m o d u l at i o n d i s t or t i on w i t h in p u ts co nsis tin g o f sine wa v e s a t tw o f r eq uen c ies, fa and fb , a n y a c t i v e de v i ce wi th n o nlin ea ri ti e s cr e a t e s d i s t o r ti o n p r o d uc ts a t s u m a nd dif f er ence f r e q uen c ies o f mfa nfb , w h er e m, n = 0, 1, 2, 3, a nd s o o n . i n t e r m o d u l a t ion disto r tio n t e r m s a r e th ose f o r which n e i t her m n o r n a r e eq ual t o zer o . f o r exa m p l e , th e s e co n d -o r d er t e r m s in c l ude (fa + fb) a nd (fa ? fb), while the thir d-o r der t e r m s in c l ude (2fa + fb), (2fa ? fb), (fa + 2fb) a nd (fa ? 2fb). the ad7760 is t e s t e d usin g t h e ccif s t anda rd , wher e tw o in p u t f r e q u e nc i e s ne a r t h e top e n d of t h e i n put b a nd w i d t h are u s e d . i n t h is c a s e , t h e s e con d -o r d er t e r m s a r e us ual l y dis t an c e d i n f r e q uen c y f r o m t h e o r ig inal si n e wa v e s, w h i l e t h e t h ir d-o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o th e in p u t f r eq uen c ies. a s a r e su lt, t h e s e co nd- and t h ird-o r der ter m s ar e sp e c if ie d s e p a r a tely . t h e ca lc u l a t ion o f t h e i n ter m o d u l a t io n disto r t i o n is as p e r t h e thd s p e c if ic a t ion, w h er e i t is t h e ra t i o o f t h e r m s s u m o f th e in d i v i d u al d i s t o r ti o n p r od uct s t o th e rm s a m p l i t ud e o f t h e s u m o f t h e f u ndam e n t als exp r es s e d i n db . i n t e g r a l n o nlin ea ri ty (inl) the maxi m u m de v i a t ion f r o m a st ra ig h t li n e p a ssin g t h r o ug h th e en d p o i n t s o f th e ad c tra n sf e r fun c ti o n . d i f f erenti a l n o n l i n e a r i ty ( d n l ) the dif f er ence b e tw e e n t h e m e as ur e d and t h e i d e a l 1 ls b c h a n g e be tw een a n y tw o a d j a cen t cod e s i n t h e a d c . off s et e r r o r the devia t ion of th e f i rs t co de t r a n si tio n (000... 000 t o 000...001) f r o m t h e ide a l (t ha t is, a g nd + 1 ls b). ga in er r o r the devia t ion of th e las t co de tra n si tion (111...1 10 t o 111...111) f r o m t h e ide a l (t ha t is, v ref ? 1 ls b), a f t e r t h e of fs et er r o r has been ad j u s t e d o u t . p o w e r su pp l y re j e c t i o n r a t i o ( p sr r ) t h e ra ti o o f th e po w e r i n th e ad c o u t p u t a t fu ll- s cale f r eq uen c y , f , t o th e p o w e r o f a 100 mv p-p sin e wa v e a p p l ie d t o th e a d c v dd s u p p l y o f fr e q u e n c y f s . t h e fr e q u e n c y o f t h i s in p u t va r i es f r o m 1 kh z t o 1 mh z. ( ) ( ) pfs pf db psrr log 10 = p f is t h e p o w e r a t f r e q ue n c y f in t h e a d c o u t p u t ; p f s is t h e p o w e r a t f r eq uen c y fs in the ad c o u t p u t .
prelim inary technical data ad7760 r e v. prn | pa ge 11 of 22 typical perf orm ance cha r acte ristics defa u l t c o n d i ti o n s: t a = 25c , tb d , u n l e ss other w is e not e d. !" !# $ % # & ' !" !# $ % # & ' fi g u r e 7 . t b d !" !# $ % # & ' !" !# $ % # & ' fi g u r e 8 . t b d !" !# $ % # & ' !" !# $ % # & ' fi g u r e 9 . t b d !" !# $ % # & ' !" !# $ % # & ' f i g u re 10. tbd !" !# $ % # & ' !" !# $ % # & ' f i g u re 11. tbd !" !# $ % # & ' !" !# $ % # & ' f i g u re 12. tbd
ad7760 prelim inary technical data r e v. prn | pa ge 12 of 22 theor y of opera tion the ad7760 em p l o y s a sig m a-de l t a con v ersion t e c h niq u e t o co n v er t t h e a n al og in p u t i n t o an e q ui valen t dig i t a l w o r d . th e m o d u l a t o r s a m p les th e in p u t wa v e fo r m an d o u t p u t s a n e q ui vale n t dig i t a l w o r d t o the dig i tal f i l t er a t a ra t e e q ual t o i cl k . d u e t o t h e hig h o v er -s a m plin g ra t e , w h ich sp r e ads t h e q u an t i za t i on n o is e f r o m 0 t o f ic l k , t h e n o is e e n erg y co n t a i n e d in th e b a nd o f in t e r e s t is r e d u ce d (f igur e 13a). t o f u r t h e r r e d u ce th e q u a n tiz a ti o n n o i s e , a hi gh o r d e r m o d u la t o r i s e m p l o y ed t o s h a p e t h e n o is e s p e c t r um; s o t h a t m o s t o f t h e no is e energ y is s h if t e d o u t o f t h e ban d o f in t e r e s t (f igur e 13b). the dig i tal f i l t e r in g whic h fol l o w s th e mo d u la to r r e m o v e s th e la rg e o u t-o f - b and q u an t i za t i on n o is e (f igur e 1 3 c) w h i l e als o r e d u cin g t h e da ta ra te f r o m f ic l k a t t h e i n p u t o f t h e f i l t er t o f ic l k /8 o r les s a t t h e o u t p u t o f t h e f i l t er , dep e n d in g on t h e de cima t i on ra t e use d . dig i t a l f i l t er in g has cer t a i n ad van t a g es o v er a n al og f i l t er in g. i t do es n o t i n t r o d uce sig n if ican t n o is e o r di sto r t i o n an d can b e made p e r f e c t l y lin e a r phas e. the ad7760 em p l o y s thr e e f i ni t e i m p u ls e res p o n s e (fir) f i l t ers in s e r i es. by usin g dif f er e n t com b in a t io ns o f de cima t i on r a t i o s a nd f i l t er s e le c t io n an d b y p a ssin g, d a t a can b e ob t a i n e d f r o m th e ad77 60 a t a la rg e ra ng e o f da ta ra t e s. m u l t i-b i t da ta f r o m th e m o d u l a t o r can be ob tain e d a t a r a t e o f 20mh z. the f i rs t f i l t er r e cei v es da ta f r o m t h e m o d u l a t o r a t 2 0mh z w h er e i t is decima t e d b y f o ur t o o u t p u t da ta a t 5m h z . this p a r t ial l y f i l t er e d da t a ca n als o b e o u t p u t a t t h is st a g e . the s e con d f i l t er al lo ws th e decima tion ra te t o b e c h os en f r o m 2 x t o 32x o r t o be ! " # $% &% '% f i gur e 1 3 . si g m a-d e l t a adc co m p lete l y b y p a s s e d . th e t h ird f i l t er has a f i xe d de cima t i on ra t e o f 2x a n d is us er p r og ra mma b l e as w e l l as ha vin g a def a u l t co nf igur a t io n. i t is des c r i b e d i n det a i l i n t h e pr o g r a mma b l e f i r f i l t er s e c t ion. this f i l t er can als o be b y p a s s ed . t a b l e x be lo w s h o w s s o m e charac t e r i s t ics o f t h e defa u l t f i l t er . the g r o u p de l a y o f t h e f i l t er is def i n e d t o b e t h e de l a y t o t h e cen t r e o f t h e im p u ls e r e s p ons e an d is e q ual to t h e com p u t a t i o n + f i l t er dela y s . the dela y u n til valid da ta is a v aila b l e (t h e d v alid s t a t us b i t is s e t) is eq ual t o 2x th e f i l t er de l a y + th e com p u t a t io n dela y . t a bl e 5. c o nf i g ur a t i o n w i t h d e fa u l t f i lt er iclk freuenc y filter 1 filter 2 filter 3 data stat e computation delay filter d e lay passband bandwidth output data rate (odr) 20 mhz bypass ed bypass ed bypass ed unfiltered 0 0 (10 mhz ) 20 mhz 20 mhz 4x bypassed bypa ssed partially filtered 0.325 1.2s 1.35 mhz 5 mhz 20 mhz 4x bypassed 2x fully fi ltered 1.075 10.8s 1 mhz 2.5 mhz 20 mhz 4x 2x bypassed partially filtered 1.35 3.6s 562.5 khz 2.5 mhz 20 mhz 4x 2x 2x fully filtered 1.625 22.8s 500 khz 1.25 mhz 20 mhz 4x 4x bypassed partially filtered 1.725 6s 281.25 khz 1.25 mhz 20 mhz 4x 4x 2x fully filtered 1.775 44.4s 250 khz 625 khz 20 mhz 4x 8x bypassed partially filtered 2.6 10.8s 140.625 khz 625 khz 20 mhz 4x 8x 2x fully filtered 2.25 87.6s 125 khz 312.5 khz 20 mhz 4x 16x bypassed partially filtered 4.175 20.4s 70.3125 khz 312.5 khz 20 mhz 4x 16x 2x fully filtered 3.1 174s 62.5 khz 156.25 khz 20 mhz 4x 32x bypassed partially filtered 7.325 39.6s 35.156 khz 156.25 khz 20 mhz 4x 32x 2x fully filtered 4.65 346.8s 31.25 khz 78.125 khz 12.288mhz 4x 8x 2x fully filtered 3.66 142.6s 76.8 khz 192 khz 12.288mhz 4x 16x 2x fully filtered 5.05 283.2s 38.4 khz 96 khz 1 2 . 2 8 8 m h z 4 x 3 2 x b y p a s s e d partially filtered 11.92 64.45s 21.6 khz 96 khz 12.288mhz 4x 32x 2x fully filtered 7.57 564.5s 19.2 khz 48 khz
preliminary technical data ad7760 rev. prn | page 13 of 22 ad7760 interface reading data the ad7760 uses a 16-bit bi-directional parallel interface. this interface is controlled by the rd /wr and cs pins. there are two read operating modes depending on the output data rate. when the ad7760 is outputting data at 5msps or less, the interface operates in a conventional mode as shown in figure 2. when a new conversion result is available, an active low pulse is output on the drdy pin. to read a conversion result from the ad7760, two 16-bit read operations are performed. the drdy pulse indicates that a new conversion result is available. both rd /wr and cs go low to perform the first read operation. shortly after both these lines go low, the databus becomes active and the 16 most significant bits (msbs) of the conversion result are output. the rd /wr and cs lines must return high for a period of tbd ns before the second read is performed. this second read will contain the 8 least significant bits (lsbs) of the conversion result along with 7 status bits. these status bits are shown in table 6. the cal bit is set to a 1 if a calibration has been performed. table 14 contains descriptions of the other status bits. table 6. status bits during data read d7 d0 dvalid ovr ufilt lpwr filtok dlok cal 0 shortly after rd /wr and cs return high, the databus will return to a high impedance state. both read operations must be completed before a new conversion result is available as the new result will overwrite the contents on the output register. if a drdy pulse occurs during a read operation, the data read will be invalid. when the ad7760 is operating in modulator data output mode, i.e. output data rate at 20mhz, a different interfacing scheme is necessary. to obtain data fr om the ad7760 in th is mode, both rd /wr and cs lines must be held low. this will bring the databus out of its high impedance state. figure 3 shows the 20mhz output data rate operation. a drdy pulse is generated for each word and the data is valid on the rising edge of the drdy pulse. this drdy pulse could be used to latch the modulator data into a fifo or as a dma control signal. shortly after the rd /wr and cs lines return high, the ad7760 will stop outputting data and the databus will return to high impedance. sharing the parallel bus by its nature, the high accuracy of the ad7760 make it sensitive to external noise sources. these include digital activity on the parallel bus. for this reason it is recommended that the ad7760 data lines are isolated from the system databus by means of a latch or buffer to ensure that there is no digital activity on the d0-d15 pins that is not controlled by the ad7760. if multiple, synchronized, ad7760 parts that share a properly distributed common mclk signal exist in a system, these parts can share a common bus without being isolated from each other. this bus can then be isolated from the system bus by a single latch or buffer. writing to the ad7760 after a reset, only a single write operation to power up the ad7760 is necessary to start the part converting on default settings. while the ad7760 is configured to convert analog signals with the default settings on reset, there are many features and parameters on this part that the user can change by writing to the device. as some of the programmable registers are 16 bits wide, to program a register requires two write operations. the first write contains the register address while the second write contains the register data. there is an exception to this when a user filter is being downloaded to the ad7760. this is dealt with in detail in the following section. the ad7760 registers section contains the register addresses and further details. figure 4 shows a write operation to the ad7760. the rd /wr line is held high while the cs line is brought low for a minimum of tbd ns. the register address is latched during this period. the cs line is brought high again for a minimum of tbd ns before the register data is put onto the databus. if a read operation occurs between the writing of the register address and the register data, the register address is cleared and the next write must be the register address again. this also provides a method to get back to a known situation if the user somehow loses track whether the next write is an address or data. it is envisaged that the ad7760 will be written to and configured on power-up and very infrequently, if at all, after that. following any write operation, the full group delay of the filter must pass before valid data will be output from the ad7760. reading status and other registers the ad7760 features a number of programmable registers. to read back the contents of these registers or the status register, the user must first write to the control register of the device setting a bit corresponding to the register they wish to read. the next read operation will then output the contents of the selected register instead of a conversion result. more information on the relevant bits in the control register is given in the ad7760 registers section.
ad7760 prelim inary technical data r e v. prn | pa ge 14 of 22 clocking the ad7760 the ad7760 r e q u ir es a n ext e r n al lo w ji t t e r c l o c k s o ur ce . this sig n a l is a p plie d t o t h e mcl k and mcl k pi ns . a n i n t e r n a l clo c k sig n a l (i c l k) is der i ve d f r o m t h e mcl k in p u t sig n a l . this i c l k con t r o ls al l th e in t e r n al o p era t ion o f th e ad7760. the maxim u m i c lk f r eq uen c y is 20mh z b u t d u e t o a n in t e r n a l clo c k divider , a ra n g e o f mclk f r e q uen c ies can b e us e d . th er e a r e t h r e e p o s s ib i l i t ies a v a i l a b l e to g e n e ra t e t h e iclk: 1. i c lk = m c l k (cd i v[1:0] = 1 0 ) 2. i c lk = m c l k / 2 (cd i v[1:0] = 00) 3. i c lk = m c l k / 4 (cd i v[1:0] = 01) th e s e o p t i on s ar e s e le c t e d f r o m t h e con t r o l r e g i s t er (s e e regist e r s e ctio n f o r f u r t h e r d e tails). on p o w e r - u p , th e d e fa ul t is i c lk = m c l k / 4 t o en s u r e tha t th e p a r t c a n ha ndle the maxim u m m c l k f r eq uen c y o f 80mh z. i f t h e us er wish es t o g e t o u t p u t da t a ra t e s eq ual t o t h os e us ed in a u dio sy s t em s, a 12.288 mh z i c lk f r eq uen c y can b e us ed . a s sh o w n in t a b l e 5, o u t p u t da ta r a t e s o f 19 2, 96 a n d 48 kh z a r e ac hieva b le wi t h this i c lk f r e q uen c y . a s m e n t ion e d p r e v io usly , t h is i c lk f r e q uen c y can b e der i ve d f r o m dif f er en t mcl k f r e q uen c ies. the mclk ji t t e r r e q u ir em e n ts dep e n d on a n u m b er o f fac t o r s a nd a r e g i ve n b y t h e fol l o w in g e q u a t i o n : 20 ) ( ) ( 10 2 db snr in rms j f osr t = os r = o v er -s am plin g r a t i o = odr f iclk f in = m a xim u m i n p u t f r eq uen c y s n r( db) = t a rg et s n r . t a k i n g an exa m ple f r o m t a b l e 5: o d r = 2.5mh z, f ic l k = 20mh z, f in (max) = 1mh z, s n r = 108db ps t rms j 79 . 1 10 10 2 8 4 . 5 6 ) ( = = this is t h e maxi m u m a l lo wa b l e clo c k ji t t e r fo r a f u l l -s ca le 1mh z in p u t t o n e wi th t h e gi v e n i c lk a n d ou t p u t da ta r a t e . t a k i n g a s e cond exa m ple f r o m t a b l e 5: odr = 4 8 k hz, f ic l k = 12.288mh z, f in (max) = 19.2kh z , s n r = 120db ps t rms j 133 10 10 2 . 19 2 256 6 3 ) ( = = the i n p u t am pli t ude als o has an ef fe c t o n t h es e ji t t e r f i gur e s. i f , for e x am pl e, t h e i n put l e vel w a s 3 d b dow n f r om f u l l - s c a l e , t h e al lo wa b l e ji t t er w o u l d b e i n cr e a s e d b y a fac t o r o f 2 in cr e a sin g t h e f i rs t exam ple t o 2.53ps rms . this is d u e t o t h e fac t t h a t t h e max i m u m sle w r a te is r e d u ce d b y a r e d u c t io n i n a m pl i t ude. f i gur e 14 a nd f i gur e 15 il l u s t ra t e this p o in t s h owin g the maxim u m s l e w ra t e o f a sin e wa v e o f th e s a m e f r eq uen c y b u t wi t h dif f er en t am pli t udes. f i gure 14. maxi mu m s l ew ra te of si n e w a ve w i th a m p l itude of 2v p k - p k f i g u re 15. m a x i mu m s l ew ra te of s a me f r equenc y s i n e w a ve wit h a m plit ud e of 1v p k -p k
prelim inary technical data ad7760 r e v. prn | pa ge 15 of 22 driving the ad7760 the ad7760 has a n o n -c hi p dif f er en tial am p l if ier . this a m plif ier wi l l op era t e w i t h a s u p p l y v o l t a g e (a v dd 3 ) f r o m 3v t o 5.5v . f o r a 4.096v r e f e r e n c e , the s u p p l y v o l t a g e m u s t be 5v . t o achi e v e t h e sp e c if ie d p e r f o r ma nce i n f u l l p o w e r m o de , t h e dif f er en t i a l a m plif ier sh o u ld b e co nf igur e d as a f i rst o r der a n t i - alias f i l t er as sho w n in f i gur e 1 6 . an y addi tio n al f i l t er in g sh o u ld b e ca r r i e d o u t i n p r e v io us st a g e s usin g lo w n o is e , hig h - p e r f o r ma n c e o p -a m p s s u ch as t h e ad8021. s u i t a b le com p on e n t val u es fo r t h e f i rs t o r der f i l t er a r e lis t e d in t a b l e 7. u s i n g t h e f i rs t r o w as an exa m ple w o u l d yie l d a 10 db a t t e n u a t io n a t t h e f i rs t al ias p o in t o f 19mh z.

f i g u re 16. d i f f e r e nt ia l a m p lif ier co nf ig ur at i o n table 7. full p o wer compo n e n t values od r v re f r in r fb c s c fb 2.5mh z 4 . 0 9 6 v 1k ? 6 5 5 ? 5 . 6 p f 3 3 p f 2.5mh z 2 . 5 v tbd ? t b d ? t b d t b d pf 48kh z 4 . 0 9 6 v tbd ? t b d ? t b d t b d pf 48kh z 2 . 5 v tbd ? t b d ? t b d t b d pf f i gur e 17 s h o w s th e sig n al condi t io nin g tha t o c c u rs usin g th e cir c ui t in f i gur e 16 wi t h a 2.5v in p u t sig n al b i as ed a r o u n d g r o u n d usin g t h e co m p onen t v a l u es a nd con d i t i o n s in t h e f i rs t r o w o f t a b l e 7. the dif f er en t i al a m plif ier wi l l alwa ys b i as t h e output s i g n a l to s i t on t h e opt i m u m c o m m on mo d e of v ref /2, in this cas e 2.048 v . th e sig n al is als o s c aled t o g i v e th e maxim u m al lo wa b l e v o l t a g e sw in g w i t h t h i s r e fer e n c e val u e . this is calc u l a t ed as 80 % o f v ref , i . e . 0.8 4.096v 3.275v p e ak t o peak o n ea c h i n p u t . ( ) % ( % ( ( ) % ( % ( ) %( %( ) %( ( ) ( ) %( %( ) %( f i g u re 17. d i f f e r e nt ia l a m p lif ier sig n a l cond it io ning t o ob ta in maxim u m p e r f o r ma n c e f r o m t h e ad7760, i t is ad vis a b l e t o dr iv e t h e ad c wi t h dif f er en t i al si g n als. h o w e v e r , i t is p o s s i b le t o dr i v e the ad7760 wi t h a sin g le ended sig n al on c e t h e comm o n mo de o f t h e sig n a l is wi t h in t h e ra n g e o f +0.7v t o +2.1v wi th v dd 3 = 5v o r +0.7 t o +1.25v wi t h v dd 3 = 3.3v . i n t h is cas e t h e o n -chi p dif f er en t i a l a m plif ier can b e us e d t o co n v er t t h e sig n al f r o m sin g le-e n d e d t o dif f er en t i al b e fo r e b e in g f e d in t o th e mo d u l a t o r in p u ts. f i gur e 18 s h o w s h o w a b i p o la r sin g le-e n d e d sig n a l b i as e d a r o u nd g r o u nd can b e us e d to dr i v e th e ad7760 wi th the us e o f a n ext e r n al o p -a m p s u c h as t h e ad8021.

f i g u re 18. sing le e n ded to d i f f e r e nt ia l convers i on
ad7760 preliminary technical data rev. prn | page 16 of 22 using the ad7760 the following is the recommended sequence for powering up and using the ad7760. 1. apply power 2. start clock oscillator, applying mclk 3. ta ke reset low for a minimum of 1 mclk cycle 4. wait a minimum of 2 mclk cycles after reset has been released. 5. write to control register 2 to power up the adc and the differential amplifiers as required. the correct clock divider (cdiv[1:0]) ratio should be programmed here also. 6. write to control register 1 to set up the output data rate. 7. ta ke sync low for a minimum of 2 mclk cycles. data can now be read from the part using the default filter, offset, gain and over range threshold values. the conversion data read will not be valid however until the group delay of the filter has passed. when this has occurred, the dvalid bit read with the data lsw will be set indicating that the data is indeed valid. the user can now download their own filter if required (see downloading a user-defined filter). values for gain, offset and over range threshold registers can be written or read at this stage. an internal calibration sequence can also be initiated at this point. bias resistor selection the ad7760 requires a resistor to be connected between the r bias pin and agnd. the value for this resistor is dependant on the reference voltage being applied to the device. the resistor value should be selected to give a current of 25a through the resistor to ground. for a 2.5v reference voltage, the correct resistor value is 100k ? and for a 4.096v reference, 160k ? .
prelim inary technical data ad7760 r e v. prn | pa ge 17 of 22 programmable fir fil ter a s p r evio us l y men t ion e d , the thir d fir f i l t er o n th e ad7760 is us er p r og ra mm a b le . th e def a u l t co ef f i cien ts t h a t a r e lo ade d o n r e s e t a r e g i v e n i n t a b l e 8. this g i v e s a f r e q uen c y r e s p o n s e s h own in f i gur e 19. th e f r eq uen c ies q u o t ed in f i gur e 19 s c ale d i r e ct l y w i th th e o u t p u t da t a r a t e . table 8. defaul t filter coefficients # d e c . val u e hex value # dec. value hex va lue 0 5 3 6 5 6 7 3 6 3 3 2 b c a 0 2 4 7 0 0 8 4 7 a b 1 a f 1 2 5 1 4 2 6 8 8 1 7 f a 5 a 0 2 5 - 7 0 9 2 2 4 0 1 1 5 0 a 2 - 4 4 9 7 8 1 4 4 4 4 a 1 9 6 2 6 - 5 8 3 9 5 9 4 0 8 e 9 1 7 3 - 1 1 9 3 5 8 4 7 4 b 6 2 0 6 7 2 7 - 1 7 5 9 3 4 4 0 2 a f 3 e 4 - 1 3 1 3 8 4 1 4 1 4 0 c 3 1 2 8 3 8 8 6 6 7 5 e e 3 b 5 6 9 7 6 3 3 4 6 a 7 3 4 e 2 9 2 9 4 0 0 0 4 7 c 7 0 6 3 2 6 8 0 5 9 3 1 d d d b 3 0 - 1 8 3 2 5 0 4 0 2 c b d 2 7 - 3 7 9 4 6 1 0 4 3 9 e 6 b 2 3 1 - 3 0 2 5 9 7 4 0 4 9 e 0 5 8 - 3 7 4 7 4 0 2 4 3 9 2 e 4 a 3 2 1 6 0 3 4 3 e a 2 9 1 5 0 9 8 4 9 1 7 0 9 d 9 3 3 2 3 8 3 1 5 3 a 2 e b 1 0 3 4 2 8 0 8 8 3 4 4 e f 8 3 4 8 8 2 6 6 1 5 8 c a 1 1 8 0 2 5 5 1 3 9 7 f 3 5 - 1 4 3 2 0 5 4 0 2 2 f 6 5 1 2 - 2 6 7 2 1 2 4 4 2 8 c 5 f c 3 6 - 1 2 8 9 1 9 4 0 1 f 7 9 7 1 3 - 1 0 5 6 6 2 8 4 1 0 1 f 7 4 3 7 5 1 7 9 4 c a 5 2 1 4 1 7 4 1 5 6 3 1 a 9 2 f b 3 8 1 2 1 8 7 5 1 d c 1 3 1 5 1 5 0 2 2 0 0 1 6 e b f 8 3 9 1 6 4 2 6 4 0 2 a 1 6 - 8 3 5 9 6 0 4 0 c c 1 7 8 4 0 - 9 0 5 2 4 4 0 1 6 1 9 c 1 7 - 1 5 2 8 4 0 0 4 1 7 5 2 5 0 4 1 - 6 3 8 9 9 4 0 0 f 9 9 b 1 8 9 3 6 2 6 1 6 d b a 4 2 4 5 2 3 4 b 0 b 2 1 9 1 2 6 9 5 0 2 1 3 5 e f e 4 3 1 1 4 7 2 0 1 c 0 2 0 2 0 4 1 1 2 4 5 6 4 6 6 d 4 4 1 0 2 3 5 7 1 8 f d 5 2 1 - 8 6 4 0 3 8 4 0 d 2 f 2 6 4 5 5 2 6 6 9 c d b d 2 2 - 6 6 4 6 2 2 4 0 a 2 4 2 e 4 6 1 5 5 5 9 3 c c 7 2 3 4 3 4 4 8 9 6 a 1 3 9 4 7 1 9 6 3 7 a b the def a u l t f i l t e r sh o u ld b e suf f icien t fo r a l m o st a l l a p pli c a t ions. i t is a s t anda rd b r ick wal l f i l t er wi t h a symm et r i cal i m p u ls e r e s p o n s e . the defa u l t f i l t er has a len g th o f 96, in n o n-aliasin g wi t h 120db o f a t t e n u a t ion a t n y q u is t. this f i l t er n o t o n l y p e r f or ms s i g n a l an t i - a l i a s i n g but a l s o suppre s s e s out - of - b a n d q u an t i za t i on n o is e p r o d uce d b y t h e a - d con v ersio n p r o c es s. an y sig n if ican t r e laxa t i on i n t h e st o p -b an d a t t e n u a t io n o r tra n si ti o n ba n d w i d t h r e la t i v e t o th e d e fa ul t f i l t e r m a y r e s u l t i n a fa i l ur e t o m e et t h e snr s p e c if ic a t io n s . i f a us er do es wis h t o cr ea t e t h eir o w n f i l t er t h en the f o l l o w in g shou l d b e note d : ? t h e f i l t e r m u s t be ev en , s y mm etri cal fir . ? the co ef f i cien ts a r e in sig n -and-ma g ni t u de fo r m a t wi t h 26 m a g n i t ude b i ts and sig n co de d as p o si t i ve=0. ? the f i l t er len g th m u s t be betw een 12 an d 96 in st eps o f 12. ? a s t h e f i l t er is s y mm et r i cal , t h e n u m b er o f co ef f i cien ts th a t m u s t be d o w n loa d e d w i ll b e h a lf th e f i l t e r le n g th . the def a u l t f i l t e r co ef f i cien ts a r e a n exam ple o f t h is wi t h o n l y 48 co ef f i cien ts lis t e d f o r a 96-ta p f i l t er . ? c o ef f i cien ts a r e wr i t t e n f r o m t h e cen t er o f im pu ls e r e s p o n s e (ad j ac en t t o t h e p o in t o f symm e t r y ) out w ard s . ? the co ef f i cien ts a r e s c ale d s o t h a t t h e i n -b an d g a in o f th e f i l t er is eq ua l t o 134217726 wi t h t h e co ef f i cien ts r o un de d t o t h e n e a r est in t e g e r . f o r a lo w p a s s f i l t er t h is is t h e e q ui v a len t o f ha ving t h e co ef f i cien ts sum a r i t hm etical l y (in c l u din g sig n ) to +67108863 (0 x3ff ffff) posi ti v e val u e o v er th e half-im p ulse-r espo n s e co ef f i cien t s e t ( m ax 48 co ef f i cien ts). an y de via t io n f r o m t h is wi l l r e su l t in a ga i n er r o r b e in g i n t r o d uce d . -160 -140 -120 -100 -80 -60 -40 -20 0 0 5 0 0 1000 1500 2000 2500 fr equency ( k hz ) a m pli t ud e ( d b ) p a s s band ri pple = 0.05 db -0.1db freque ncy = 1.004mhz -3db frequ enc y = 1.06mhz s t opband = 1.25mhz fi g u r e 1 9 . d e f a u l t f i l t e r fr e q u e n c y r e s p o n s e ( 2 . 5 m h z o d r ) the p r o c e d ur e fo r do wnlo adin g a us er -def i n e d f i l t er is det a i l e d in t h e d o w n lo adin g a u s er - d ef in e d f i l t er s e c t i o n.
ad7760 prelim inary technical data r e v. prn | pa ge 18 of 22 downloading a user-defined fil ter a s p r e v io us l y men t ion e d , t h e f i l t er co ef f i cien ts a r e 27 b i ts in len g th; o n e sig n a nd 26 ma g n i t ude b i ts. s i n c e t h e ad7760 has a 16-b i t p a ral l e l b u s, th e co ef f i cien ts a r e p a dded wi t h 5 ms b zeros t o g e n e r a t e a 32 -b i t w o r d and sp li t in t o tw o 16-b i t w o r d s f o r do wnlo ading. th e f i rs t 16 -b i t wo r d f o r eac h co ef f i cien t be com e s (00000, s i g n b i t, m a g n i t ude[25:16]), while th e s e co nd w o r d becom e s ( m a g ni t u de [15:0]). t o en s u r e tha t a f i l t er is do wn lo ade d cor r e c t l y , a ch e c ksum m u st a l s o b e gen e r a t e d and d o w n l o a d ed f o l l o w i n g th e fi n a l c o e ffi c i e n t . t h e c h e c k s u m i s a 16-b i t w o r d g e nera t e d b y s p li t t in g eac h 32-b i t w o r d men t ione d a b o v e in t o 4 b y tes a nd s u mming al l b y t e s f r o m al l co ef f i cien ts u p t o a maxim u m o f 192 b y t e s (48 co ef f i cien ts 4 b y t e s). th e s a me c h ec ks um is g e n e r a t e d in ter n al l y in th e ad7760 a nd co m p a r ed wi th th e ch eck s um do w n l o a d ed . th e d l _ o k b i t in t h e s t a t us reg i s t e r is s e t if t h e s e tw o che c ks u m s a g r e e . th e fol l o w in g is t h e p r o c e d ur e fo r do wnlo adin g a us er f i l t er : 1. w r i t e t o c o n t r o l reg ist e r 1 s e t t i n g t h e dl_f i l t b i t an d als o t h e co r r e c t f i l t er len g t h b i ts co r r es p o n d i n g t o t h e len g t h o f t h e f i l t er a b o u t t o b e do wnlo ade d (s e e t a b l e 9). 2. w r i t e t h e f i rs t half o f t h e c u r r en t co ef f i cien t da t a (00000, s i g n b i t, m a g n i t ude[25:16]). th e f i rs t co ef f i cien t t o b e wr i t t e n m u s t b e t h e one ad jace n t t o th e po i n t o f f i l t er sym m e tr y . 3. w r i t e t h e s e cond half o f t h e c u r r en t co ef f i cien t da t a (m a g ni t u de [15:0]). 4. rep e a t s t eps 2 and 3 fo r e a ch co ef f i cien t. 5. w r i t e t h e 16- b i t ch e c ks u m . 6. ther e a r e tw o m e t h o d s t o v e r i f y t h a t t h e f i l t er coe f f i ci e n t s ha v e been d o w n l o a d ed co rr ectl y : a. re ad t h e s t a t us reg ist e r che c ki n g t h e d l_o k b i t. b. s t a r t r e adin g da t a an d obs e r v e t h e st a t us o f t h e d l_ok b i t. table 9. filter length values flen[3:0] num coef fs filter length 0 0 0 0 d e f a u l t d e f a u l t 0 0 0 1 6 1 2 0 0 1 1 1 2 2 4 0 1 0 1 1 8 3 6 0 1 1 1 2 4 4 8 1 0 0 1 3 0 6 0 1 0 1 1 3 6 7 2 1 1 0 1 4 2 8 4 1 1 1 1 4 8 9 6 i t s h o u ld b e b o r n e i n mi n d t h a t sin c e t h e us er co ef f i cien ts a r e s t o r ed in ram, th ey w i ll be c l ea r e d a f t e r a res e t op e r a t i o n or a los s o f p o w e r .. ex ample fil t er do wnl o ad the fol l o w in g is a n exa m ple o f do wnlo ading a s h o r t us er d e fi n e d fi l t e r w i t h 2 4 - ta p s . t h e fr e q u e n c y r e s p o n s e i s s h o w n i n f i gur e 20. -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 100 20 0 300 400 500 6 0 0 freq uen c y ( k hz) a m plitude (db) fi g u r e 2 0 . 2 4 - t a p f i r fr e q u e n c y r e s p o n s e the co ef f i cien ts fo r t h e f i l t er a r e lis t e d i n t a b l e 10. th e co ef f i cien ts a r e in sh o w n f r o m t h e ce n t er o f sy mmet r y o u twa r ds. the ra w co ef f i cien ts w e r e g e n e r a t e d usin g a co mm er cial l y a v a i lab l e f i l t er de sig n t o ol and s c ale d a p p r o p r i a t e l y s o th eir s u m eq uals +67108863 (0x3ff ffff). table 10. 2 4 -t ap fir coe fficients c o e f f r a w s c a l e d 1 0.365481974 53188232 2 0.201339905 29300796 3 0.009636604 1402406 4 -0.075708848 -11017834 5 -0.042856209 -6236822 6 0.019944246 2902466 7 0.036437914 5302774 8 0.007592007 1104856 9 -0.021556583 -3137108 10 -0.024888355 -3621978 11 -0.012379538 -1801582 12 -0.001905756 -277343
preliminary technical data ad7760 rev. prn | page 19 of 22 table 11 shows the hex values (in sign and magnitude format) that are downloaded to the ad7760 to realize this filter. the table is also split into the bytes which are all summed to produce the checksum. the checksum generated from these coefficients is 0x0e6b. table 11. filter hex values coeff word 1 word 2 byte 1 byte 2 byte 3 byte 4 1 03 2b 96 88 2 01 bf 18 3c 3 00 15 66 26 4 04 a8 1e 6a 5 04 5f 2a 96 6 00 2c 49 c2 7 00 50 e9 f6 8 00 10 db d8 9 04 2f de 54 10 04 37 44 5a 11 04 1b 7d 6e 12 04 04 3b 5f what follows is a list of 16-bit words that the user would write to the ad7760 to set up the adc and download this filter assuming an output data rate of 1.25mhz has already been selected. 0x0001 address of control register 1 0x8079 control reg data; dl filter, set filter length = 24, set output data rate = 1.25mhz 0x032b first coefficient, word 1 0x9688 first coefficient, word 2 0x01bf second coefficient, word 1 0x183c second coefficient, word 2 0x0404 twelfth (final) coefficient, word 1 0x3b5f final coefficient, word 2 0x0e6b checksum wait tbd xs for ad7760 to fill remaining unused coefficients with zeros. 0x0001 address of control register 0x0879 control reg data; set read status and maintain filter length and decimation settings. read contents of status register. check bit 7 (dl_ok) to determine that the filter was downloaded correctly.
ad7760 preliminary technical data rev. prn | page 20 of 22 ad7760 registers the ad7760 has a number of user-programmable registers. the contro l registers are used to set the decimation rate, the filter configuration, the clock divider etc. there are also digital gain, offset and over-range threshold registers. writing to these registers involves writing the register address first, then a 16-bit data word. register addresses, details of individual bits and defaul t values are given here. table 12. control register 1 (address 0x0001, default value 0x001a) msb lsb dl filt rd ovr rd gain rd off rd stat cal sync flen3 flen2 flen1 flen0 byp f3 byp f1 dec2 dec1 dec0 bit mnemonic comment 15 dl filt 1 download filter. before downloading a user defined filter, this bit must be set. the filter length bits must also be set at this time. the write operations that follow will be interprete d as the user coefficients fo r the fir filter until all the coefficients and the checksum have been written. 14 rd ovr 1 , 2 read overrange. if this bit has been set, the next read operation will output the contents of the overrange threshold register instead of a conversion result. 13 rd gain 1 ,2 read gain. if this bit has been set, the next read operation will output the contents of the digital gain register. 12 rd off 1 ,2 read offset. if this bit has been set, the next read opera tion will output the contents of the digital offset register. 11 rd stat 1 ,2 read status. if this bit has been set, the next read operation will output the conten ts of the status register. 10 cal 1 calibration. setting this bit will init iate an internal calibration routine. this routine will take 14ms with a 20mhz iclk. 9 sync 1 synchronize. setting this bit will initiate in internal synchronisation routine. setting this bit simultaneously on multiple devices will synchronize all filters. 8-5 flen3:0 filter length bits. these bits must be set when the dl filt bit is set and before a user defined filter is download ed. 4 byp f3 bypass filter 3. if this bit is a 0, filter 3 (programmable fir) will be bypassed. 3 byp f1 bypass filter 1. if this bit is a 0, filter 1 will be bypassed . this should only occur when the user requires unfiltered modulator data to be output. 2-0 dec2:0 decimation rate. these bits set the decimation rate of filter 2. all zeros impli es that the filter is bypassed. a value of 1 corresponds to 2x decimation, a value of 2 corresponds to 4x and so on up to the maximum value of 5, corresponding to 32x decimation. 1 bits 15-9 are all self clearing bits. 2 only one of the bits 14-11 may be set in any write operation as they all determine the contents of the next read operation table 13. control register 2 (address 0x0002, default value 0x009b) msb lsb 0 0 0 0 0 0 0 0 0 0 cdiv1 cdiv0 pd lpwr 1 d1pd bit mnemonic comment 5-4 cdiv1:0 clock divider bits. these set the divide ratio of the mclk signal to produce the internal iclk. setting cdiv[1:0] = 00 divides the mclk by 2, setting cdiv[1:0] = 01 divides mclk by 4. if cdiv[1:0] = 10 then the mclk frequency is equal to the iclk. cdiv[1:0] = 11 is not allowed. 3 pd power down. setting this bit powers down th e ad7760 reducing the power consumption to tbd w. 2 lpwr low power. if this bit is set, the ad7760 is operating in a low power mode. the power consumption is reduced for a 6db reduction in noise performance. 1 write a 1 to this bit. 0 d1pd differential amplifier power down. setting this bit powers down the on-chip differential amplifier.
preliminary technical data ad7760 rev. prn | page 21 of 22 table 14. status register (read only) msb lsb pa rt 1 pa rt 0 die 2 die 1 die 0 dvalid lpwr ovr dl ok filter ok u filter byp f3 byp f1 dec2 dec1 dec0 bit mnemonic comment 15,14 part1:0 part number. these bits will be constant for the ad7760. 13-11 die2:0 die number. these bits will reflect the current ad 7760 die number for identification purposes within a system. 10 dvalid data valid. this bit corresponds to the dvalid bit in the status wo rd output in the second 16-bit read operation. 9 lpwr low power. if the ad7760 is operating in low power mode, this bit is set to a 1. 8 ovr if the current analog input exceeds the curre nt overrange threshold, this bit will be set. 7 dl ok when downloading a user filter to th e ad7760, a checksum is generated. this checksum is compared to the one downloaded following the coefficients. if these checksums agree, this bit is set. 6 filter ok when a user-defined filter is in use, a checksum is generated when the filter co efficients pass thro ugh the filter. this generated checksum is compared to the one downloaded. if th ey match, this bit is set. 5 u filter if a user-defined filter is in use, this bit is set. 4 byp f3 bypass filter 3. if filter 3 is bypassed by setting the rel evant bit in control register 1, this bit is also set. 3 byp f1 bypass filter 1. if filter 1 is bypassed by setting the rel evant bit in control register 1, this bit is also set. 2-0 dec2:0 decimation rate. these correspond to the bits set in control register 1. . non bit-mapped registers offset register (address 0x0003, default value 0x0000) the offset register uses 2s complement notation and is scaled such that 0x7fff (maximum positive value) and 0x8000 (maximum negative value) correspond to an offset of +0.78125% and -0.78125% respectively. offset correction is applied after any gain co rrection. using the default gain value of 1.25 and assuming a reference voltage of 4.096v, the offset correction range is approximately 25mv. gain register (address 0x0004, default value 0xa000) the gain register is scaled such that 0x8000 corresponds to a gain of 1.0. the default value of this register is 1.25 (0xa000). this gives a full scale digital output when the input is at 80% of v ref . this ties in with the maximum analog input range of 80% of v ref pk-pk. over range register (addre ss 0x0005, default value 0xcccc) the over range register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. this is prior to any gain scaling or offset adjustment. the default value is 0xcccc which corresponds to 80% of v ref (the maximum permitted analog input voltage) assuming v ref = 4.096v, the bit will then be set when the input voltage exceeds approximately 6.55v pk-pk differential. note that the over-range bit is also set immediately if the analog input voltage exceed s 100% of v ref for more than 4 consecutive samples at the modulator rate.
ad7760 prelim inary technical data r e v. prn | pa ge 22 of 22 outline dimensions 1 12 13 24 25 36 37 48 bo tt om view 7.0 (0.276) bsc sq 5.25 (0.207) 5.10 (0.201) sq 4.95 (0.195) 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) 0.50 (0.020) 0.40 (0.016) 0.30 (0.012) pin 1 indica t o r to p view 6.75 (0.266) bsc sq 5.5 (0.217) ref 0.25 (0.010) min 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) 0.70 (0.028) max 0.65 (0.026) nom 0.05 (0.002) 0.01 (0.0004) 0.0 (0.0) 0.20 (0.008) ref 0.50 (0.020) bsc 12max 0.90 (0.035) max 0.85 (0.033) nom 0.30 (0.012) 0.23 (0.009) 0.18 (0.007) f i gure 21. 4 8 -l ead f r a m e chip s c a l e p a ckage [lfcs p ] (c p - 48)d i m ensi ons sho wn in m i l l i m ete r s 1 16 17 33 32 48 49 64 12.0(0.47) bsc 10.0(0.39) bsc 0.50 (0.02) bsc 0.22 0.05 (0.0087 0.002) seating plane 1.60 (0.063) max 0.60 0.15 (0.024 0.006) 12 o typ 0 o 3.5 o 3.5 o 0.15(0.006) 0.05(0.002) top view 6.0(0.235) bsc f i gure 22. 6 4 -l ead thin q u ad f l at p a c k (e xposed p a ddl e) [ t qfp ] (sv - 64) d i m ens i ons sh o w n in m i l l i m eters ordering guide model temperature r a nge package descri ption package option ad7760bcp C40c to +85c lead fra me chip scale package cp-48 AD7760BSV C40c to +85c thin quad flat pack, exposed paddle sv-64 ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . prin ted in th e u.s . a.

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